| Author | Henkes, Tim; Reith, Steffen; Stöttinger, Marc; Herfurth, Norbert; Panic, Goran; Wälde, Julian; Buschkowski, Fabian; Sasdrich, Pascal; Lüth, Christoph; Funck, Milan; Kiyan, Tuba; Weber, Arnd; Boeck, Detlef; Rathfelder, René; Grawunder, Torsten |
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| Date | 2024 |
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| Type | Conference Paper |
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| Abstract | The project "Hardening the value chain through open-source, trustworthy EDA tools and processors (HEP)" uses open-source, free components and tools for the production of a prototypical security chip. A design flow using only free and open tools from the abstract description in SpinalHDL via OpenROAD down to the GDS-file for tape-out has been established, and first ASICs produced at IHP. The prototypical hardware security module (HSM) produced in this way provides, among other things, a processor based on VexRiscv, a cryptographic accelerator and masking of cryptographic keys. The open development tools used in the process were integrated into a common environment and expanded to include missing functionality. Subsequently, the whole tool chain and its peripherals are wrapped into a new Nyx container. The easy accessibility of the used process significantly reduces the learning curve for chip design. Additionally, we provide tools for formal verification and masking against side-channel attacks in our design flow. Interest in the results of project HEP has been shown in publications in which industrial partners participated, such as Elektrobit, Hensoldt Cyber, IAV, Secure-IC and Swissbit Germany. |
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| Conference | Design, Automation & Test in Europe Conference & Exhibition 2024 |
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| Url | https://publica.fraunhofer.de/handle/publica/470489 |
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